Fast LDPC GPU Decoder for Cloud RAN

نویسندگان

چکیده

The graphical processing unit (GPU), as a digital signal accelerator for cloud RAN, is investigated. This letter presents new design 5G NR low-density parity check code decoder running on GPU. algorithm flexibly adaptable to GPU architecture achieve high resource utilization well low latency. It improves the layered by increasing parallelism single word. flexible (on 24 core GPU) was found have $5\times $ higher throughput compared recent flooding and notation="LaTeX">$3\times field programmable gate array (FPGA) (757K gate). exhibits 1/3 decoding power efficiency of FPGA typical general-purpose processors. For rapid deployment flexibility, GPUs may be suitable RAN accelerators.

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A New LDPC Coder/Decoder for PLC

Adding the ability of LDPC to an OFDM system gives rise to a robust and suitable technique for broadband PLC. However, despite LDPC codes performing admirably for large block sizes, real time operation and low computational effort require small and medium sized codes, which tend to be affected by channel SNR and errors in channel equalization. This paper deals with improvements made to an OFDM ...

متن کامل

Hardware Architecture for Modified Sequential LDPC Decoder

Iterative decoding of Low Density Parity Check (LDPC) codes using the Parity Likelihood Ratio (PLR) algorithm have been proved to be more efficient compared to conventional Sum Product Algorithm (SPA). However, the nature of PLR algorithm tends to put numerious pieces of data to this decoder and perform computation intensive operations, which is a major challenge for building a practical real-t...

متن کامل

LDPC Decoder LLR Stopping Criterion

The log-likelihood ratio test on a single check node within the LDPC decoder is monitored to develop a stopping criterion for the decoder that is better than previous stopping criteria, without sacrificing the BER performance. Simulation results are presented for the transmission of the rate 1 2 (288, 576) WiMAX 802.16e LDPC code digits using binary phase shift keying (BPSK) over an AWGN channel.

متن کامل

Efficient VLSI Parallel Implementation for LDPC Decoder

Iterative decoding of Low Density Parity Check (LDPC) codes using the Parity Likelihood Ratio (PLR) algorithm have been proved to be more efficient compared to conventional Sum Product Algorithm (SPA). However, the nature of PLR algorithm tends to put numerious pieces of data to this decoder and perform computation intensive operations, which is a major challenge for building a practical real-t...

متن کامل

High-Throughput Irregular LDPC Decoder

Abstract— This paper presents a high-throughput area-efficient decoder design for the irregular Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEEE Embedded Systems Letters

سال: 2021

ISSN: ['1943-0671', '1943-0663']

DOI: https://doi.org/10.1109/les.2021.3052714